This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-385299, filed on Dec. 19, 2000, and No. 2001-362666, filed on Nov. 28, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a display device for driving signal lines by turning ON/OFF a switching circuit based on shift pulses outputted from a shift resister.
2. Related Background Art
A thin and lightweight display device is widely used in portable electrical equipments such as a mobile phone, a note-type computer and a portable television. Especially, it is possible to accomplish a thinner and lighter liquid crystal display with a low power consumption. Therefore, liquid crystal displays have been widely developed, and it is possible to buy a liquid crystal display with high resolution and large screen size at a relatively low price.
Among liquid crystal displays, a liquid crystal display of an active matrix type, in which TFTs(Thin Film Transistors) are provided in the vicinity of intersections of signal lines and scanning lines excels in color quality. Furthermore, there is less residual image in such a liquid crystal display. Because of this, the liquid crystal display of the active matrix type is expected to become far popular in near feature.
A conventional liquid crystal display of the active matrix type has a driving circuit for driving signal lines and scanning lines formed on a substrate, which is different from a pixel array substrate, on which the signal lines and the scanning lines are arranged. Because of this, it has been difficult to downscale the entire liquid crystal display. Therefore, manufacturing processes for integrally forming the driving circuit on the pixel array substrate are now being intensely developed.
Because liquid crystal displays are used for various applications, there is an increased demand to switch driving directions of the signal lines either from left to right or from right to left of the screen. When such a switching operation becomes possible, even if a direction to train a digital camera does not coincide with a direction to see the monitor of the camera, it is possible to operate the camera without an uncomfortable feeling, thereby improving operationality and enhancing a commercial value of the camera.
If the above-mentioned switching becomes possible in the liquid crystal display for a personal computer, it is possible to compensate for display irregularity occurring in a certain scanning direction by switching the scanning direction, thereby improving the display quality.
In order to switch the driving direction of the signal lines, a shift register capable of bidirectionally shifting has to be provided in the signal line driving circuit.
FIG. 8 is a circuit diagram showing a configuration of a conventional bidirectional shift register 40. The shift register 40 of FIG. 8 has a plurality of register circuits 2 connected in cascade. Each of the registers 2 is composed of a latch circuit 44 having clocked inverters 41 and 42 and an inverter 43, and clocked inverters 45 and 46 for switching the shift direction of the shift register 40. A NAND gate 47 is provided for each of the register circuits 2.
The NAND gate 47 executes a NAND operation between a shift pulse outputted from the corresponding register circuit 2 and the shift pulse outputted from the register circuit 2 of the preceding stage. Outputs of the NAND gates 47 are used to control ON/OFF of analog switches not shown in FIG. 8. When the analog switch turns ON, an analog pixel voltage on a video bus is provided to the corresponding signal line.
FIG. 9 is an operational timing chart of input/output signals of the shift register 40 of FIG. 8. As shown in FIG. 9, the shift direction of the shift register 40 is switched by a logic of a shift direction control signal. FIG. 9 shows an example of performing a forward shift when the shift direction control signal LR1 is in low level and the another shift direction control signal LR2 is in high level, and performing an inverse direction shift when the signal LR1 is in high level and the signal LR2 is in low level.
Because the shift register 40 of FIG. 8 is a so-called shift register of a half clock type, which shifts the shift pulses by every half cycle of clock signals, circuit configurations of odd stages and even stages are different from each other. Therefore, the timing of the output signal of each of the register circuits 2 constituting the shift register 40 has to be adjusted by using the NAND gate 47. As a result, the number of gates existing after the start signal is inputted to the shift register 40 and before a shift pulse obtained by shifting the start signal is inputted to an analog switch via the circuit of FIG. 8 increases, thereby increasing delay of the shift pulses relative to the clock signal.
Therefore, there is a likelihood that the display is influenced by a fluctuation of properties of the TFTs in the signal driving circuit, thereby deteriorating image quality. More specifically, a plurality of analog switches arranged adjacent to each other turn ON at the same time, the load of the video bus fluctuates, and the potential on the video bus causes an overshoot or undershoot. When the potential on the video bus fluctuates, before the potential returns to the original potential, the analog switch, which should essentially be turned ON, turns OFF. Therefore, an erroneous potential is held at the signal line connected to the analog switch, thereby causing a block irregularity.
In order to avoid such a problem, a pulse cut circuit is often provided at a subsequent stage of the NAND gate 47 of FIG. 8. FIG. 10 is a circuit diagram showing an internal configuration of a conventional pulse cut circuit 50, and FIG. 11 is an operational timing chart of the circuit of FIG. 10.
The pulse cut circuit 50 of FIG. 10 has inverters 51-53 and a NAND gate 54 having three input terminals. Each NAND gate 54 executes a logical operation based on the shift pulse of the present stage and inverse signals of the shift pulses of the preceding and next stages.
The NAND gate 54 of FIG. 10 changes a rising edge position and a trailing edge position of the shift pulse in the present stage and outputs a pulse having a narrower pulse width than the shift pulse of the present stage.
With the pulse cut circuit 50 of FIG. 10, regardless of the shift direction of the shift register 40, it is possible to constantly narrow the pulse width of the shift pulse of the present stage by a certain amount.
However, when a timing at which the analog switch turns from ON to OFF is controlled by the pulse cut circuit 50 of FIG. 10, a timing at which the analog switch turns from ON to OFF fluctuates due to the pulse width of the shift pulses of the preceding and the subsequent stages and the properties of the TFTs. Therefore, there is a likelihood that a plurality of analog switches turn ON at the same time.
Thus, if a timing at which the analog switch turns from ON to OFF staggers, display irregularities appear more clearly, as compared with the case in which the timing changing from ON to OFF staggers, thereby also decreasing a timing margin.
An object of the present invention is to provide a display device in which display quality is excellent and a timing margin is large.
In order to achieve the foregoing object, a display device according to the present invention, comprising:
signal lines and scanning lines in a matrix form;
display elements arranged in the vicinity of intersections of the signal lines and the scanning lines;
a signal line driving circuit configured to drive each of the signal lines; and
a scanning line driving circuit configured to drive each of the scanning lines;
wherein said signal line driving circuit includes:
a shift resister, having a plurality of resister circuits connected in cascade, capable of allowing a clock signal to shift in two-way directions between these resister circuits, configured to output from each of the resister circuits, shift pulses obtained by allowing the clock signal to shift;
a pulse width adjusting circuit configured to adjust pulse widths of said shift pulses; and
a switching circuit configured to turn ON/OFF based on the output of said pulse width adjusting circuit, and to provide a pixel voltage to the corresponding signal line to the ON period,
wherein said plurality of resister circuits are composed of the same circuit configuration, respectively; and
said pulse width adjusting circuit adjusts the pulse width of said shift pulse so that more than one of said switching circuits do not turn on at the same time.
Furthermore, a display device according to the present invention, comprising:
signal lines and scanning lines in a matrix form;
display elements arranged in the vicinity of intersections of the signal lines and the scanning lines;
a signal line driving circuit configured to drive each of the signal lines; and
a scanning line driving circuit configured to drive each of the scanning lines;
wherein said scanning line driving circuit includes:
a shift resister, having a plurality of resister circuits connected in cascade, capable of allowing a clock signal to shift in two-way directions between these resister circuits, configured to output from each of the resister circuits, shift pulses obtained by allowing the clock signal to shift; and
a pulse width adjusting circuit configured to adjust pulse widths of said shift pulse,
wherein said plurality of resister circuits are composed of the same circuit configuration, respectively; and
said pulse width adjusting circuit adjusts the pulse width of said shift pulse so that more than one of said switching circuits do not turn on at the same time.